The present invention relates to a processing apparatus and a method of modifying a system configuration, and more particularly to a processing apparatus and a method of modifying a system configuration well suited to hot plugging of a device in a PCI Express system.
Conventionally, for standards of a bus for connecting a CPU with an I/O device inside a computer, parallel bus standards called PCI, which are standardized by the Peripheral Component Interconnect Special Interest Group (PCI-SIG), are commonly employed. Today, advanced versions of PCI, including PCI-X in which the transmission speed is improved, and PCI Express in which the parallel bus is serialized for communication using packets between connected devices, are standardized.
In the following description, a system comprised of mutually connected devices in PCI Express will be referred to as PCI Express system, several kinds of devices to be connected will be referred to as PCI Express devices, a bus for connecting the devices will be referred to as PCI Express bus, and packets for use in communication will be referred to as PCI Express packets. An exemplary conventional PCI Express system is disclosed in Non-patent Document 1 (“PCI Express Base Specification Revision 1.1,” PCI-SIG, Mar. 28, 2005, pp. 30, 319-330, 349-361.).
Referring to FIG. 16, the conventional PCI Express system is comprised of: a root complex 1300 that connects to a CPU 1100 via a host bus and to a memory 1200 via a memory bus, for serving as a “root” of the tree topology of PCI Express; a PCI Express switch 5100 for providing a fan-out function to the PCI Express bus; and I/O devices 1400 connected via the PCI bus. In general, the side adjacent to the root complex 1300 of the tree topology of PCI Express is referred to as upstream, and that adjacent to the I/O devices 1400 is referred to as downstream. While in FIG. 16, three I/O devices are connected to the PCI Express switch 5100, the number of the I/O devices 1400 that can be connected is not limited to three. Reference numeral 1000 designates configuration software provided in the computer for the PCI Express system. Here, software held in the BIOS and OS for configuring the PCI device are generically called configuration software.
Referring to FIG. 17, the PCI Express switch 5100 comprises an upstream PCI-PCI bridge 1501, an internal PCI bus 1503, and downstream PCI-PCI bridges 1505. The upstream PCI-PCI bridge 1501 and downstream PCI-PCI bridges 1505 comprise respective configuration registers 1502 for retaining information on PCI Express resource spaces connected downstream of the respective bridges. The PCI Express resource spaces are spaces occupied under several addresses used in a PCI Express system. An attention button 17001 is a button for use by a user when he/she starts a hot-plugging operation.
FIG. 18A and FIG. 18B are block diagrams showing the internal arrangement of the configuration register. The configuration register includes two types: Type 1 and Type 0, and the configuration register of Type 1 is used in a PCI-PCI bridge, and that of Type 0 is used in an I/O device.
The configuration registers of Type 1 and Type 0 retain in common a device ID 18011, a vendor ID 18012, and a class code 18013. The device ID designates a device number specific to a vendor, the vendor ID designates the number of a manufacturer, and the class code designates a device attribute. The configuration software 1000 can identify what kind of a device it is by looking up these three registers.
The configuration register of Type 1 additionally has a lower limit value 18001 and an upper limit value 18002 of the bus number required in packet routing to a downstream bus, a lower limit value 18003 and an upper limit value 18004 of a 32-bit I/O space, and a lower limit value 18005 and an upper limit value 18006 of a 32-bit memory space, and in some cases, a lower limit value 18007 and an upper limit value 18008 of a 64-bit I/O memory space. These values are written in by the configuration software 1000 during initial configuration of PCI Express. Moreover, the configuration register of Type 1 comprises a hot-plugging register 18014 as standard.
On the other hand, the configuration register of Type 0 retains at least one base address register 18021 indicating two address spaces, i.e., a memory space and an I/O space, required by an I/O device. The base address register 18021 is also used by the configuration software 1000 for writing a base address when allocating an address space for the I/O device.
The conventional PCI Express system having such an arrangement operates as follows:
Upon start of a PCI Express initial configuration cycle, all PCI Express devices present in a PCI Express system are searched for by the configuration software 1000. In particular, all PCI buses in the system are scanned, and each slot in every PCI bus is checked for the attribute of a PCI Express device occupying the slot. Then configuration is achieved by sequentially allocating a PCI Express resource space required by each PCI Express device that is found. For example, in the PCI Express system shown in FIG. 16, the I/O devices 1400 connected downstream of the PCI Express switch 5100 are assigned with respective resource spaces that they require, and according to the size of the spaces assigned, values in the configuration registers 1502 of the downstream PCI-PCI bridges 1505 and upstream PCI-PCI bridge 1501 of the PCI Express switch 5100 are set, including the lower limit value 18001 and upper limit value 18002 of the bus number, the lower limit value 18003 and upper limit value 18004 of the 32-bit I/O space, the lower limit value 18005 and upper limit value 18006 of the 32-bit memory space, etc.
Communication from the CPU 1100 to an I/O device 1400, etc. is executed according to the configuration registers 1502 set as described above, in the following manner: For communication from the CPU 1100 to an I/O device 1400 connected to the PCI Express switch 5100, a PCI Express packet is generated at the root complex 1300 at the command by the CPU 1100, and is transmitted to the upstream PCI-PCI bridge 1501 in the PCI Express switch 5100. The upstream PCI-PCI bridge 1501 looks up the configuration register 1502, and decides whether the destination of the PCI Express packet is connected to a PCI Express bus downstream of the bridge itself. If the destination is connected to a PCI Express bus downstream of the bridge itself, the PCI Express packet is broadcast to all the downstream PCI-PCI bridges 1505. Each downstream PCI-PCI bridge 1505 decides whether the destination is connected to a PCI Express bus downstream of the bridge itself via the same function as that of the aforementioned upstream PCI-PCI bridge 1501, and transfers the PCI Express packet to a PCI Express bus to which the destination I/O device 1400 connects.
When communication is made from an I/O device 1400 connected to the PCI Express switch 5100 to the CPU 1100, the aforementioned procedure for PCI Express packet transfer from the CPU 1100 to an I/O device 1400 is inverted. Specifically, the upstream PCI-PCI bridge 1501 and downstream PCI-PCI bridge 1505 each transfer a PCI Express packet to the upstream of the bridge itself if the destination of the packet does not correspond to a PCI Express resource space downstream of the bridge itself, as indicated by its configuration register 1502. When the PCI Express packet is to be transferred from the downstream PCI-PCI bridge 1505 to the upstream PCI-PCI bridge 1501, uni-casting is employed instead of broadcasting.
Moreover, PCI Express provides a hot-plugging function for active connection/disconnection of a plug of an I/O device to/from an unoccupied slot (see Non-patent Document 1, for example). Hot plugging in the conventional PCI Express operates as follows: When an I/O device 1400 is inserted into a downstream slot of a downstream PCI-PCI bridge 1505, a link is established between the downstream PCI-PCI bridge 1505 and I/O device 1400, and synchronization of electric signals, exchange of credit information and the like are automatically activated. Subsequently, upon a press of the attention button 17001 by the user, the downstream PCI-PCI bridge 1505 turns the hot-plugging register 18014 on, and at the same time generates an interrupt to the CPU 1100. Triggered by the interrupt, the configuration software 1000 is invoked to configure the inserted I/O device 1400 and clear the hot-plugging register 18014. After completion of the configuration, the inserted I/O device 1400 is enabled.
In addition, a technique of dynamically modifying the configuration of a computer system is disclosed in Patent Document 1 (JP-P1989-76252A), although this is not a technique relating to PCI Express or hot plugging. This conventional technique involves registering I/O devices connected to the computer system and those anticipated to be installed in the future together into an I/O table beforehand as actual devices and reserved devices, respectively, providing a flag in the I/O table for identifying each I/O device as being in an actual device status or in a reserved device status, and changing each device from an actual one to a reserved one or vice versa by setting/resetting the flag during the operation of the system. The I/O table is a table that is registered in an external storage device as an object and then developed onto a main storage device by executing system generation processing, for being looked up by the OS in controlling the I/O device.
Hot plugging is a technique that allows an I/O device or the like to be physically attached or removed while other devices in a system are in service. In the conventional PCI Express system, the primary hot-plugging function works in a case, for example, in which the I/O device 1400 that was attached to the PCI Express switch 5100 in FIG. 16 during the initial configuration cycle is replaced by a similar I/O device 1400 because the former one has broken down. However, it is substantially impossible to hot-plug a new I/O device into a slot that was unoccupied during the initial configuration cycle.
The reason of this is that during the initial configuration cycle by the configuration software 1000 of the PCI Express system provided in a conventional computer (which cycle will be sometimes referred to as PCI Express initial configuration cycle hereinbelow), a bus number is assigned to the PCI Express bus, and a device number, a function number, a 32-bit I/O space, a 32-bit memory space, and if necessary, a 64-bit memory space, are assigned to the PCI Express switch and I/O device, in a sequential manner; however, they are not assigned to an unoccupied slot. Thus, when an I/O device is inserted into an unoccupied slot in the PCI Express switch, a PCI Express resource space to be assigned to the inserted I/O device may interfere with that for another device having been using that space, even if the configuration software 1000 of the PCI Express system is adapted for hot plugging of an I/O device defined by the PCI-SIG Standards. Therefore, installation of an I/O device into an unoccupied slot requires reconfiguration of the whole PCI Express system, including the configuration registers held by the upstream PCI-PCI bridge and downstream PCI-PCI bridges in the PCI Express switch, and the base address registers held by other I/O devices containing information on the PCI Express resource spaces that have been allocated, and thus, a desired I/O device cannot be hot-plugged while services provided by other I/O devices are continued.
For a similar reason to the above, it is difficult in the conventional PCI Express system to hot-plug an I/O device into a root complex, hot-plug a PCI Express switch into a PCI Express switch, hot-plug a PCI Express switch into a root complex, and hot-plug a downstream PCI-PCI bridge into an upstream PCI-PCI bridge in a PCI Express switch.
Moreover, for hot plugging of devices other than I/O devices, i.e., for hot plugging of a PCI Express switch into a PCI Express switch and into a root complex, and hot plugging of a downstream PCI-PCI bridge into an upstream PCI-PCI bridge in a PCI Express switch, the configuration software 1000 that merely supports hot plugging of I/O devices among those defined in the PCI-SIG Standards cannot configure a hot-plugged PCI Express switch or downstream PCI-PCI bridge, this being one of the reasons why these kinds of hot plugging are difficult.
On the other hand, for I/O devices etc. anticipated to be installed in the future, Patent Document 1 discloses the idea of defining them beforehand as reserved devices in the I/O table looked up by the OS. Now consider that this idea be applied to a PCI Express system. Since the I/O table as disclosed in Patent Document 1 is a set of data looked up by the OS to control I/O devices, the table corresponds to a PCI data structure representing the PCI topology of a PCI system in terms of a PCI Express system. Thus, when the idea of Patent Document 1 is applied to a PCI Express system, the PCI data structure is added with a flag for discriminating each device between an actual one and a reserved one, and the device is changed from an actual one to a reserved one or vice versa by setting/resetting the flag during an operation of the system. However, this method poses a problem that a device to be inserted must be identified beforehand, and also a problem that, since the PCI data structure is created by the configuration software 1000 during the initial configuration and looked up in subsequent control, the existing configuration software 1000, and hence, the OS itself, should be modified so that it can handle the flag for discriminating each I/O device between an actual one and a reserved one.